1. Field of the Invention
The present invention generally relates to a semiconductor device and, more particularly, to a non-volatile memory device and a fabrication method thereof.
2. Description of the Related Art
As non-volatile memory devices have become more highly integrated, the need has increased for reducing the area occupied by a driving circuit for operating a memory cell. There has also been a need for an improvement in an intergate dielectric layer formed between a floating gate and a control gate such that a voltage induced to the floating gate can be maintained at a suitable level for a device""s operating characteristics while a low voltage is applied to the control gate. This is so that the level of the voltage of the floating gate, which is induced when a high voltage is applied to the control gate for programming a device, is affected by a coupling ratio of the intergate dielectric layer. Accordingly, improving the coupling ratio of the intergate dielectric layer is needed.
In addition, during the process of erasing a conventional non-volatile memory device, a path of electrons is established toward a source node. That is, due to a small area through which the electrons pass, current density becomes concentrated in the area, thereby deteriorating a tunneling oxide layer, i.e., a tunneling insulating layer. Thus, a new non-volatile memory device capable of preventing deterioration of the tunneling insulating layer and having improved reliability is needed.
The present invention is directed to overcoming or at least reducing the effects of one or more of the problems set forth above.
Briefly, in accordance with one aspect of the present invention, there is provided a non-volatile memory device comprising a semiconductor substrate, a bit line, a word line which crosses the bit line, a first memory cell in a region of the semiconductor substrate where the word line crosses the bit line, and a second memory cell in a region of the semiconductor substrate where the word line crosses the bit line.
Briefly, in accordance with another aspect of the present invention, there is provided a non-volatile memory device comprising: a plurality of isolation regions formed on a semiconductor substrate to define active regions; a plurality of common source regions formed in the semiconductor substrate, extending in a column direction; a plurality of drain regions formed in the active regions alternately with the common source regions, being separated from the common source regions by a predetermined interval; a tunneling insulating layer formed on the active regions including the common source regions and the drain regions; a plurality of floating gates formed on the tunneling insulating layer, arranged in the column direction along with each common source region, such that each of the common source regions has a pair of the floating gates centered around it; intergate dielectric layers formed on the floating gates; a plurality of control gates formed on the intergate dielectric layers, parallel to the common source regions, each control gate overlapping pairs of floating gates adjacent in the column direction; and a plurality of bit lines formed perpendicular to the plurality of control gates, each bit line being connected to the plurality of drain regions.
Briefly, in accordance with another aspect of the present invention, there is provided a method for fabricating a non-volatile memory device, comprising: forming isolation layers on a semiconductor substrate to define active regions; forming floating gate layers on the active regions while a tunneling insulating layer is interposed therebetween; forming common source regions in a column direction, each crossing the floating gate layers so as to divide each of the floating gate layers and the isolation layers into two parts; forming intergate dielectric layers and control gate layers on the divided floating gate layers; patterning the control gate layers, the intergate dielectric layers and the divided floating gate layers to complete control gates, intergate dielectric layers and floating gates, wherein each control gate is parallel to one of the common source regions and overlaps a pair of the floating gates adjacent in a column direction, and wherein the pair of the floating gates centers around one of the common source regions; and forming bit lines connected to drain regions adjacent to the floating gates.